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Stories related to "Rotor CPU - 16 RISC cores in Verilog" across the full archive.
The Megalomaniac Bore: Write your own Virtual CPU in C++ (4001 CPU)
(megalomaniacbore.blogspot.co.uk)
As background, the lowRISC project aims to produce a fully open-source SoC using the RISC-V instruction set architecture and bring it to volume production. We've just released this document to describe in more detail our plans for tagged memory (not exactly the rebirth of the LISP machine, but has u...
I discovered [Project IceStorm](http://www.clifford.at/icestorm/) while searching for FOSS FPGA toolchains. Clifford Wolf and Mathias Lasser worked to reverse-engineer the "iCE40" FPGA stick. The device itself is small, simple, and cheap, which made reverse-engineering it more feasible. Unfortunatel...
Super simple explanation of latest cpu security issues