🦞🌯 Lobster Roll

Thread

DAC Pavilion: RISC-V: Instruction Sets Want To Be Free (youtube.com)
L 8 pts 0 comments by inactive-user Jul 12, 2016 hardwarevideo thread

Stories related to "DAC Pavilion: RISC-V: Instruction Sets Want To Be Free" across the full archive.

DAC Pavilion: RISC-V: Instruction Sets Want To Be Free (youtube.com)
L 8 pts 0 comments by inactive-user Jul 12, 2016 hardwarevideo Systems / Low-Level / OSMaker / DIY / Hardware thread
Jack Whitham: RISC instruction sets I have known and disliked (blog.jwhitham.org)
L 18 pts 1 comments by chadski May 2, 2016 assembly Systems / Low-Level / OS thread
An Empirical Comparison of the RISCV and AArch64 Instruction Sets (dl.acm.org)
L 5 pts 1 comments by brucehoult Nov 15, 2023 assemblyhardwarepdfscaling Systems / Low-Level / OSMaker / DIY / HardwareProductivity / Career / Business thread
Interesting because it's examining not just program size or number of instructions, but the Critical Path Length (the longest path of instructions where each instruction uses the result of the previous one) and the Instruction Level Parallelism (how wide a CPU you need to get the fastest execution t...
Design of the RISC-V Instruction Set Architecture (eecs.berkeley.edu)
L 12 pts 2 comments by gandro May 1, 2016 assemblyhardwarepdf Systems / Low-Level / OSDesign / UX / VisualizationMaker / DIY / Hardware thread
Moxie Mixie: Frustrating Remote Attackers with Container Specific Instruction Sets (moxielogic.org)
L 4 pts 1 comments by trn Sep 21, 2017 assemblyprogrammingsecurity Systems / Low-Level / OSProgramming (General)Security / Privacy thread
RISC-V: The Free and Open RISC Instruction Set Architecture (riscv.org)
L 7 pts 0 comments by twopoint718 Jan 3, 2018 hardware Systems / Low-Level / OSMaker / DIY / Hardware thread
How the JVM compares your strings using the craziest x86 instruction sets (jcdav.is)
L 14 pts 0 comments by av Jan 7, 2018 assemblyjava Systems / Low-Level / OSProgramming (General) thread
customasm: Assembler for custom instruction sets (github.com)
L 3 pts 2 comments by eterps Jun 22, 2018 assembly Systems / Low-Level / OS thread
Small Assets without the Headache – Minification made easy with Elm 0.19 (elm-lang.org)
L 23 pts 13 comments by ehamberg Aug 21, 2018 elmrelease Programming Languages / CS Theory thread
RISC-V Instruction Set Simulator Built For Education (github.com)
L 8 pts 1 comments by learnbyexample Jul 30, 2020 assemblyprogramming Systems / Low-Level / OSProgramming (General) thread
RISC-V Vector Instructions vs ARM and x86 SIMD (medium.com)
L 23 pts 11 comments by ethoh Jan 6, 2021 compscihardware Systems / Low-Level / OSProgramming Languages / CS TheoryMaker / DIY / Hardware thread
Why did I catch s*** for my use of the RISC-V SFENCE.VMA instruction? (blog.stephenmarz.com)
L 6 pts 0 comments by ethoh Feb 1, 2021 hardwareosdev Systems / Low-Level / OSMaker / DIY / Hardware thread
Capability Hardware Enhanced RISC Instructions (CHERI) (cl.cam.ac.uk)
L 17 pts 15 comments by quad Jan 20, 2022 hardware Systems / Low-Level / OSMaker / DIY / Hardware thread
Attempt at making an instruction reference guide for RISC-V (sr.ht)
L 5 pts 3 comments by icefox Apr 26, 2022 assemblyrelease Systems / Low-Level / OS thread
Code Density Compared Between Way Too Many Instruction Sets (portal.mozz.us)
L 33 pts 24 comments by sunset Jul 27, 2022 hardwareperformance Programming (General)Data / Databases / InfrastructureMaker / DIY / Hardware thread
Intel Sunsets Network Switch Biz, Kills RISC-V Pathfinder Program (tomshardware.com)
L 1 pts 0 comments by chrispickard Jan 27, 2023 networking Systems / Low-Level / OSProgramming (General)Data / Databases / Infrastructure thread
The legend of "x86 CPUs decode instructions into RISC form internally" (fanael.github.io)
L 49 pts 35 comments by Freaky Jun 18, 2023 assemblyhardware Systems / Low-Level / OSMaker / DIY / Hardware thread
riscv-fs: F# RISC-V Instruction Set formal specification (github.com)
L 9 pts 2 comments by Decabytes Jul 29, 2023 dotnet Systems / Low-Level / OSProgramming (General) thread
ARMfuck: Turing completeness from two RISC instructions (kellanclark.github.io)
L 17 pts 3 comments by calvin Sep 26, 2023 assembly Systems / Low-Level / OSProgramming Languages / CS Theory thread
Synthesize instruction datasets from PDFs for LLM Fine-tuning (medium.com)
HN 1 pts 0 comments by gauravvij137 Jul 31, 2024 AI / Machine Learning thread
Faulty instructions in C910 RISC-V CPUs (ghostwriteattack.com)
HN 77 pts 34 comments by johndoe0815 Aug 7, 2024 thread
Faulty instructions in Alibaba's T-Head C910 RISC-V CPUs blow away all security (theregister.com)
HN 10 pts 3 comments by thebeardisred Aug 7, 2024 Security / Privacy thread
Accelerate RISC-V Instruction Set Simulation by Tiered JIT Compilation (dl.acm.org)
HN 4 pts 1 comments by matt_d Oct 19, 2024 thread
GhostWrite: Exploiting CPU Bugs in RISC-V Vector Instructions [video] (youtube.com)
HN 4 pts 0 comments by lauriewired Nov 22, 2024 Systems / Low-Level / OSSecurity / Privacy thread
Visualize RISC-V Vector Memory Instructions (myhsu.xyz)
HN 4 pts 0 comments by mshockwave Jan 6, 2025 thread
Customasm: Assembler that allows you to provide your own custom instruction sets (hlorenzi.github.io)
HN 2 pts 0 comments by ingve Jan 12, 2025 thread
Customasm – An assembler for custom, user-defined instruction sets (github.com)
HN 73 pts 17 comments by zdw Jan 12, 2025 thread
Capability Hardware Enhanced RISC Instructions (en.wikipedia.org)
HN 1 pts 0 comments by mepian Jan 25, 2025 Maker / DIY / Hardware thread
RISC-V CPU Design – Lec 5 – Design Top Level and Testbench, Instruction Decode (youtube.com)
HN 3 pts 0 comments by marcux95 Mar 5, 2025 Systems / Low-Level / OS thread
RISC-V with Linux 6.15 Adds Support for BFloat16 "BF16" Instructions (phoronix.com)
HN 2 pts 0 comments by jrepinc Apr 6, 2025 Systems / Low-Level / OS thread